Storage elements are used in integrated circuits (IC) to store data as a logic state (either a “zero” or a “one”). The most basic standard cells used for storage elements are transparent latches and D-flip-flops (DFFs). Both of these storage elements use simple regenerative feedback with passgates or tristate buffers to control writing data into the element (the transparent state for a latch) versus retaining the data in the element (the latched state for a latch).
Storage elements are expected to reliably store the written data so that the correct data can be later retrieved for use. However, there are several noise sources or noise injection mechanisms that can disturb the stored data which will later give errors when reading the data. Background radiation (e.g., cosmic radiation), power supply noise and crosstalk noise from adjacent switching signals are examples of noise injection mechanisms that can disturb the stored data. Cosmic radiation, in the form of alpha particles or neutrons can inject noise into the storage elements that may upset the data stored therein. When the data is upset (i.e., changed from one logical state to another logical state), it is referred to as a Single Event Upset (SEU). Errors caused by SEUs are also referred to as soft errors since the errors are generally unrepeatable and occur randomly throughout a device. The rate at which a design is expected to have soft errors is referred to as the Soft Error Rate (SER).
Reducing power consumption by the ICs can increase the sensitivity of stored data to the various noise injection mechanisms. With reductions in IC supply voltage to reduce overall chip power, many storage elements can become exponentially more sensitive to the noise sources. This can be particularly true at voltage levels proposed for low voltage state retention intended to reduce leakage in the state retaining storage elements.
To combat the sensitivity to the noise sources, new storage architectures are being developed to reduce the likelihood of an error. Each of the new architectures need to be analyzed for noise sensitivity to demonstrate their noise immunity. The transistor architectures used in the conventional storage elements have remained relatively unchanged for 20 years. The noise sensitive nodes in these storage elements are well understood. Latches and traditional DFFs have had their noise sensitivity (calculated in terms of SER) performed by hand analysis which is time consuming and error prone.
Additionally Static Random Memories, or SRAMs, have been analyzed for Static Noise Margin (SNM) to evaluate their robustness to disturbances during their normal operation. This analysis is also performed manually and assumes a traditional SRAM bit cell architecture for the analysis. Other architectures will require independent analysis to determine which nodes to test for noise sensitivity. With the development of new architectures to improve SER and overall noise immunity (mostly due to low Vdd levels), analysis will be needed to determine noise sensitivity. Therefore, an architecture independent methodology for analyzing noise sensitivity is needed in the art.